The present disclosure relates generally to semiconductor design, and more particularly to device performance variation due to shallow trench isolation (STI) induced oxide layer stresses. Still more particularly, the present disclosure relates to the circuit and method of using dummy devices to eliminate the STI induced oxide layer stresses on the semiconductor operational devices, thereby eliminating operational device mismatch and increasing semiconductor performance.
In analog or high speed digital design, such as phase lock loops (PLL) circuitry, serial-deserial designs, analog-to-digital converters, or digital-to-analog converters, device matching is extremely important to attain the required circuit performance. Conventionally, the uneven device performance due to optics or others is called “proximity effect” in which the device's physical proximity in an area may affect the exposure dose during lithography. This proximity effect is more clearly shown in devices placed close to the edges. The etch rate may also be affected during the etching process due to the device's physical location. Varying either the exposure dose or the etch rate from one device to another device can result in a mismatch of device characteristics and therefore performance. This occurs because the printed figures of each device vary in size due to the varying exposure rate or etch rate. However the “Shallow Trench Isolation” (STI) process used in today's semiconductor fabrication processes often induces oxide layer stresses around the STI border. Since the STI border confines the active region therein, these oxide layer stresses result in uneven device performance near the STI border. The device mismatch is due to the “stress-incurred-by-trench-isolation effect”. The devices near the edges of the “active region” have different performance levels (e.g., as represented by Idsat) from those of the other internal devices that are farther away from the edges.
Desirable in the art of high frequency analog and digital designs are new designs that eliminate the “stress-incurred-by-trench-isolation effect” around the STI edges to further reduce device mismatch and increase semiconductor performance.